Instruction Wake-Up in Wide Issue Superscalars

While the central window implementation in a superscalar processor is an effective approach to waking up ready instructions, this implementation does not scale to large instruction window sizes as those that are required by wide issue superscalars of the future. We propose a new wake-up algorithm that dynamically associates explicit wake-up lists with executing instructions according to the dependences between instructions. Instead of repeatedly examining a waiting instruction for wake-up till it can be issued, this algorithm identifies and considers for wake-up a fresh subset of waiting instructions from the instruction window in each cycle. This subset of instructions are the ones present in the wake-up lists of completing instructions. The direct wake-up microarchitecture (DWMA) that we present is able to achieve approximately 80%, 75% and 63% of the performance of a central window processor at high issue widths of 8, 16 and 32 respectively when an effective memory disambiguation mechanism [13] is employed for load speculation. In contrast, the wake-up algorithm proposed in constructing the dependence-based microarchitecture (DBMA) [15] can only achieve approximately 62%, 46% and 45% of the performance of a central window processor at issue widths of 8, 16 and 32. Thus the DWMA processor greatly outperforms the DBMA processor.